Many of the previous generations of data storage devices had memory qualification issues with memories exhibiting single-bit errors. For example, some memory controllers use vertical or horizontal parity as an Error Detection Code (EDC) for verifying data integrity within the data buffer. Therefore, single-bit errors were fatal errors. The data buffer is used to cache customer data on read and writes to the media. The data buffer may also be used as a random access memory for the controller microprocessor, and as instruction storage for microprocessor program code.
As memory geometries continue to shrink and the operating speed/frequency of the device continue to increase, the rate of soft-errors also increases. Design implementations, where single-bit errors are fatal and can occur, are undesirable, and in some applications even unacceptable. An effective method to minimize failure rate due to soft-errors is through the utilization of an Error Correction Code (ECC).
Many of the data storage devices with ECC implementation utilize two or more separate memory chips in the data buffer: one or more for storing the data, and an additional one for storing the associated ECC. However, the use of multiple memory chips can increase cost and/or decrease operation efficiency.
Recently, devices that utilize a single chip in the data buffer to store both data and ECC have been introduced. Examples of such devices are illustrated in U.S. Pat. No. 6,353,910 entitled “Method and apparatus for implementing error correction coding (ECC) in a dynamic random access memory utilizing vertical ECC storage” issued to Carnevale, et al., dated Mar. 5, 2002, and U.S. Pat. No. 6,526,537 entitled “Storage for generating ECC and adding ECC to data” issued to Kishino, dated Feb. 25, 2003, each of which is incorporated by reference in its entirety for all purposes. Many of these devices employ “vertical” ECC that store data and ECC on a single memory device. Typically, the data and its corresponding ECC are stored as a continuous chain of bits on the memory array. Since the completed ECC codeword (data+ECC) is not typically 2N in size, memory locations within prescribe storage field in the memory that are not completely filled up by the ECC codeword are left unused, and thus, wasted. In addition, vertical ECC requires the system to perform address translations to skip over the ECC redundancy and the unused memory, in order to make the memory appear to be contiguous to the system application. This can result in lower system performance and/or inefficient use of memory resources.
Therefore, there is a need to improve ECC implementation in data buffers. In particular, the ability to improve the system operation efficiency while at the same time minimizing production cost (e.g., utilizing less components, etc.) may be particularly desirable.